1. Field of the Invention
The present invention relates to a communication control system and apparatus for performing communication via a clock signal line and a data signal line.
2. Related Background Art
In recent years, the number of output/drive devices such as a display device, a stepping motor, an electromagnetic clutch, and a solenoid or input/sensor devices such as an operation switch, a photointerruptor, and a mechanical binary switch has tended to increase to improve the performance of an image forming apparatus such as a copying machine. Accordingly, the number of signal lines for transmitting control signals in such systems has increased. This results in serious problems including an increase in size and weight of bundled signal lines, degradation in assembly/decomposition properties and reliability, and an increase in cost.
To solve these problems, a serial communication system is proposed in which communication substations each addressed to a unique address are arranged at various points in the system. At least one serial data line and one serial communication synchronous clock line are extracted from a main controller for controlling the entire system. The communication substations are sequentially cascade-connected to perform serial data transmission/reception between a desired communication substation and the main controller.
Such a conventional serial communication system will be described with reference to FIG. 7 which is a block diagram showing the arrangement of the conventional serial communication system. Referring to FIG. 7, a main controller 1 controls the entire image forming apparatus. A host microcomputer (to be referred to as a host hereinafter) 2 serves as the control center of the main controller 1. A serial controller 3 is coupled to the host 2 via buses and serves as a master controller for serial communication. Communication substations (relay substations) 4 and 5 are set at various points in the system. Serial communication substation ICs 6 and 7 are mounted in the communication substations 4 and 5, respectively.
In this example, one serial communication substation IC 6 is an input IC exclusively used for reception, i.e., the input IC fetches binary data from various input devices such as a photointerruptor (sensor) and transfers the data to the serial controller 3 of the host 2. The other serial communication substation IC 7 is an output IC exclusively used to output data, i.e., the output IC receives data from the serial controller 3 of the host 2 and outputs the binary data to various drive devices such as a clutch. In this example, one serial communication substation IC 6 is addressed to address 0, and the other serial communication station IC 7 is addressed to address 1. Each 8-bit packet of communication data is made to correspond to an input port or an output port.
This system also includes a +5V power supply 8 for logic circuits, a data line (DATA) 9 for serial communication, a synchronous clock line (CLK) 10, a ground line (GND) 11, a +24V power supply 12 for drive devices, and a ground line (GND) 13. The main controller 1 and the communication substations 4 and 5 are cascade-connected via these lines. Particularly, in the system of this example, the data line 9 and the synchronous clock line 10 directly cascade-connect the serial controller 3 of the host 2 to the serial communication substation ICs 6 and 7 of the communication substations 4 and 5, and the serial communication substation IC at the intermediate position transmits the output from the preceding stage to the next stage via an internal buffer in real time, as shown in FIG. 7.
The operation of the serial communication system having the above arrangement will be described next with reference to a communication format shown in FIG. 8. To acquire the value of the photointerruptor connected to bit 0 of address 0, the host 2 issues a predetermined command to the serial controller 3 via an address bus (detailed description of the actual form of the command will be omitted). In response to the command, the serial controller 3 generates a desired number of synchronous clocks and transmits the synchronous clocks to the synchronous clock line 10. The serial controller 3 also executes the following serial data transmission/reception operation on the data line 9. Each substation fetches data at the rising of the synchronous clock. Upon detecting data of xe2x80x9cLxe2x80x9d low together with the clock during waiting for communication, the substation recognizes the start of a communication frame.
At the first clock, a start bit of xe2x80x9cLxe2x80x9d for declaring the start of a communication frame is output. In this example, the logical level in the noncommunication state of the data line 9 is xe2x80x9cHxe2x80x9d high. At the next clock, an R/W bit for defining a mode requested by the serial controller 3 for this frame, i.e., a data input mode or a data output mode, is transferred. In this example, when this bit is at xe2x80x9cHxe2x80x9d, a read mode wherein the serial controller 3 receives data from the substation is set. When this bit is at xe2x80x9cLxe2x80x9d, a write mode wherein the serial controller 3 outputs data is defined. Since the input IC is set at address 0, the serial controller 3 sets this bit at xe2x80x9cHxe2x80x9d, as a matter of course.
In synchronism with the next four clocks, address 0 indicating the desired communication substation is serially transferred. All substations monitor the transferred data, and substation 0 whose self address coincides with the desired communication station address on the serial data is involved in subsequent communication. Substations having addresses different from the desired communication station address buffer the clocks and transmit them to the subsequent stages (in the direction away from the serial controller 3). In the read mode, the data line 9 buffers data from the subsequent stages and transmits it to the preceding stages. In the write mode, the data line 9 buffers data from the preceding stages and transmits it to the subsequent stages. Address 0, i.e., the designated station neglects (releases) data from the subsequent stage and serially transmits 8-bit data from the self input port in synchronism with the next eight clocks. The serial controller 3 receives the 8-bit serial data and recognizes the desired photointerruptor data at bit 0.
Almost the same procedure can be used when the host 2 drives a clutch connected to bit 0 of the output IC at address 1. The host 2 writes address 1 and issues the data and the data request command to the serial controller 3 via a bus (when data other than data at bit 0 of address 1 need not be changed, the same data as in the previous processing must be written in fact, and these data are transmitted to the serial controller 3).
The serial controller 3 transmits the necessary number of synchronous clocks to the clock line 10, as in the above processing. The serial controller 3 sequentially transmits a start bit, a write mode bit, address 1 as the 4-bit target address, and 8-bit write data. Only a substation at address 1 designated by the address bits fetches the 8-bit data on the data line 9 and outputs the data to the output port at the end of communication. In the read mode, data up to address bit A3 is output from the serial controller 3, and data bits D0 to D7 are output from the substation IC 6 or 7 to the serial controller 3. The serial controller 3 outputs clocks corresponding to one frame. The substation IC 6 or 7 outputs data bits D0 and D7 in synchronism with these clocks.
In serial communication following the above procedure, data of a plurality of bits can be transmitted/received to/from the communication substations arranged at various points in the system, so the number of signal lines for transmitting control information can be substantially reduced.
In the above-described prior art, however, the substation ICs only execute, as frame synchronization for serial data transmission/reception, simple sequence processing using synchronous clocks with reference to the start bit because of restrictions on cost whereby synchronization is maintained. Neither a variety of determination processing operations using a timer or a microcomputer for measuring frame time nor frame synchronization using a frame synchronous line different from the serial line is performed.
As shown in FIG. 9, when two noise components are mixed into the clock line in the transmission mode, and sequence processing of the substation advances by two steps from the original clock cycle, the frame ends before the end of the normal clock cycle in the substation. If transmission data bit D6 synchronizing with a subsequent normal clock is at xe2x80x9cLxe2x80x9d unexpectedly, the substation erroneously recognizes the bit data as the start of a new communication frame. Sequence processing progresses in synchronism with the remaining clocks, and even when the normal clock cycle is ended, processing continues to wait for next synchronous clocks to perform remaining sequence processing. When synchronous clocks of a new normal frame are generated, the remaining sequence processing starts, so the substation continues data reception in erroneous frame units.
As shown in FIG. 10, when six noise components are mixed, and accidentally, data bit D2 is at xe2x80x9cLxe2x80x9d, data bit D3 is at xe2x80x9cHxe2x80x9d, data bits D4 to D6 are at xe2x80x9cLxe2x80x9d, and data bit D7 is at xe2x80x9cHxe2x80x9d, the substation at address 1 is to output the data to the serial data line. Assume that the first data bit is at xe2x80x9cLxe2x80x9d, and the serial controller 3 outputs data of level xe2x80x9cHxe2x80x9d to the serial data line because the serial controller 3 considers that communication is ended (FIG. 10). In this case, a potential difference of 25 V is generated on the serial data line, and the IC may be destroyed.
It is an object of the present invention to provide a communication control system and apparatus which solve the above problems.
It is another object of the present invention to provide a communication control system and apparatus capable of canceling erroneous recognition of the start of data in a second communication apparatus, which occurs when noise or the like is mixed into a clock signal line.
Other objects and features of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings.